Xiaokun Yang, Ph.D.

Biography

Dr. Xiaokun Yang received his Ph.D. from the Department of Electrical and Computer Engineering (ECE) at Florida International University (FIU) in 2016 and his dual M.S. from the Department of ECE at FIU and the Department of Software Engineering at Beihang University in China in 2007. From 2007 to 2012, he worked as a senior ASIC design/layout engineer at Advanced Micro Devices (AMD), China Electronic Corporation (CEC), and PowerLayer MicroSystems (PLM).

His research interests include FPGA Acceleration on AI/ML, HW/SW Co-Design on FPGA, and System-on-Chip (SoC) Architecture on IoT. As the first author or corresponding author, Dr. Yang has published more than 50 papers, including three patents, more than 15 peer-reviewed journals, and more than 30 prestigious international conferences. He has served on several journal reviewers, including IEEE Trans. on Computer, IEEE Trans. on VLSI, and IEEE Trans. on Education, and numerous conference committees including ISVLSI, ACAI, MicDAT, and Nanoarch.

Curriculum Vitae

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Areas of Expertise

• Integrated circuit design and verification
• FPGA acceleration on AI and ML
• System-on-Chip (SoC) Architecture on IoT

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Publications

• I. Westby, X. Yang, et al., "Exploring FPGA Acceleration on a Multi-Layer Perceptron Neural Network for Digit Recognition," The Journal of Supercomputing (J SUPERCOMPUT) , Under Review, 2020.
• X. Yang , "Bridging the Gap Between Academia and Industry Needs with An Open Source Platform in Teaching Digital System Design," IEEE Trans. on Education (ToE) , Second Round, 2020.
• H. He, X. Yang, et al., "Iterated Dilated Convolutional Neural Networks for Word Segmentation," Neural Network World (NNW) , Second Round, 2020.
• X. Zhang, X. Fu, J. Lu, X. Yang, I. Unwala, "Face Recognition using Deep k-Nearest Neighbors in Intelligent Safety and Security Monitoring System," Multimedia Systems, (M SYST), Second Round, 2020.
• X. Yang , S. Sha, I. Unwala, and J. Lu, "Towards Third-Part IP Integration: A Case Study of High-Throughput and Low-Cost Wrapper Design on A Novel IBUS Architecture," IET Computers & Digital Techniques (IET-CDT) , Accepted, 2020.
• X. Yang and S. Sha, "Exploiting Energy-Quality (E-Q) Tradeoffs on Approximate FPGA Designs of Scalable Sequential Circuits," Journal of Circuits, Systems and Computers (JCSC) , Accepted, 2020.
• S. Sha, Ajinkya S. Bankar, X. Yang , W. Wen, and G. Quan,, "On Fundamental Principles for Thermal-Aware Design on Periodic Real-Time Multi-Core Systems," ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol. 25, No. 2, 2019.
• X. Yang , Y. Zhang, and L. Wu, "A Scalable Image/Video Processing Platform with Open Source Design and Verification Environment," 20th Intl. Symposium on Quality Electronic Design (ISQED 2019) , PP. 110-116, 2019.
• K. Vaca, A. Gajjar, and X. Yang , "Real-Time Automatic Music Transcription (AMT) with Zync FPGA," IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , PP. 378-384, 2019.
• Y. Zhang, X. Yang , L. Wu, and J. Andrian, "A Case Study On Approximate FPGA Design With an Open-Source Image Processing Platform," IEEE Computer Society Annual Symposium on VLSI (ISVLSI) , Student Forum, 2019.
• X. Yang , W. Wen, and M. Fan, "Improving AES Core Performance via An Advanced IBUS Protocol," ACM Journal on Emerging Technologies in Computing (JETC) , Vol. 14, No. 1, PP. 61-63 , Jan. 2018.
• X. Yang , N. Wu, and J. Andrian, "Comparative Power Analysis of An Adaptive Bus Encoding Method on The MBUS Structure," Journal of VLSI Design , Vol. 2017, Article ID 4914301, PP. 1-7, May 2017.
• M. Fan, Q. Han, and X. Yang , "Energy Minimization for On-Line Real-Time Scheduling with Reliability Awareness," Elsevier Journal of Systems and Software (Elsevier JSS) , Vol. 127, PP. 168-176, May 2017.
• X. Yang and W. Wen, "Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs)," The 22nd Asia and South Pacific Design Automation Conference (ASP-DAC 2017) , 2017.
• X. Yang and X. He, "Establishing a BLE Mesh Network using Fabricated CSRmesh Devices," The 2nd ACM/IEEE Symposium on Edge Computing (SEC 2017), Article No. 34, 2017.
• A. Gajjar, Y. Zhang, and X. Yang , "Demo Abstract: A Smart Building System Integrated with An Edge Computing Algorithm and IoT Mesh Networks," The Second ACM/IEEE Symposium on Edge Computing (SEC 2017), Article No. 35, 2017.
• X. Yang , N. Wu, and J. Andrian, "A Novel Bus Transfer Mode: Block Transfer and A Performance Evaluation Methodology," Elsevier, Integration, the VLSI Journal, Vol. 52, PP. 23-33, Jan. 2016.
• X. Yang and J. Andrian, "A Configurable and Synthesizable On-Chip Bus Architecture for Integrating Industrial Standard IPs," 2016 Design Automation Conference (DAC 2016) , WIP, 2016.
• X. Yang and J. Andrian, "A High Performance On-Chip Bus (MSBUS) Design and Verification," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (TVLSI), Vol. 23, Issue: 7, PP. 1350-1354, Sept. 2015.
• X. Yang and J. Andrian, "A Low-Cost and High-Performance Embedded System Architecture and An Evaluation Methodology," IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2014 - Best Ph.D Forum Paper Award) , PP. 240-243, 2014.

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Courses (Current Academic Year)

• CENG 5534: Adv. Digital Syst. Design
• CENG 4266: Senior Project
• CENG 3316: Electronics
• CENG 3116: Lab for Electronics

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Research Projects

Hardware acceleration on AI and ML 

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Awards and Accomplishments

• PI: Cisco Research & Open Innovation, Pending, 2017-2018
• PI: Faculty Research and Support Funds (FRSF), 2017-2018
• PI: Faculty Development Funds: ICAC2017, ASAP2017, SEC2017
• NSF Travel Grant, IEEE Intl. Conf. on Autonomic Computing (ICAC), 2017
• NSF Travel Grant, ACM/IEEE Symposium on Edge Computing (SEC 2017), 2017
• Section Chairs: ICCAS2018, IEEE Innovation and Automation Conference, etc.
• TPC member: MicDAT2018; Nanoarch2017; WCSE2018; etc.
• Journal Reviewer: TVLSI; TII; IET CDT; Integration, the VLSI; etc.

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